1. Field of the Invention
The invention relates generally to integrated CMOS (Complimentary Metal Oxide Semiconductor) circuits, and more particularly to circuit design techniques which reduce output ringing in very fast CMOS output buffers.
2. Description of the Prior Art
The need for increasing levels of throughput and improved performance in CMOS systems requires high speed and high dynamic drive current for CMOS output buffers that transfer signals from chip to circuit board or to back planes. This high speed and high drive can be easily achieved by modern submicron CMOS processing, but there are a few undesirable side effects.
With current technology, all internal chip nodes can slew very fast, resulting in a higher rate of change of current (di/dt) in all switching transistors. Since output devices are designed large to handle high levels of dynamic current, their di/dt rates can be very high. Chips that have several outputs switching simultaneously can have a total di/dt in the common ground or power lead inductances of over 500 mA/ns, and can develop large transient potential differences between the chip power traces and the external power connections. (The term "lead" inductance refers to the series combination of bonding wire, package pin inductance and inductance of the metal power bussing on the chip itself.)
FIG. 1 shows a prior art CMOS output driver arrangement comprising a buffer 10. Package lead inductances are represented as equivalent inductances L1, L2 and L3. An external load capacitance, C.sub.L, is typically 50 picofarads (pfd). In Order to construct a high-speed driver, an NMOS transistor 12 and a PMOS transistor 14 should be sized large enough to dynamically sink or source about 100 milliamps. A typical high-speed CMOS chip will have many such drivers that all share common on-chip power and ground rails, e.g., nodes 16 and 18. A particular area of concern is the case where most of the outputs simultaneously switch from logic HIGH to LOW by turning on transistors 12. This will generate a voltage fluctuation of the on-chip node 16 ground compared to an external system ground 20. This condition is commonly known as "ground bounce". Also, when many outputs simultaneously switch from LOW to HIGH by turning on transistors 14, there will be a "Vcc bounce" of node 18.
FIG. 2 shows some representative "bounce" signals 30 on nodes 16 (waveform 32) and 18 (waveform 34) when many buffer circuits 10 are switching simultaneously. The major problem caused by these bounce signals is that they can feed through to the outputs of any quiescent buffers sharing nodes 16 and 18. If a quiescent buffer is supposed to have its output at ground, it will, instead, have an output signal that looks like waveform 32 having a pulse amplitude "A". Likewise, if a quiescent buffer is supposed to have its output at Vcc, it will, instead, have an output signal that looks like waveform 34 having a pulse amplitude "B". If amplitudes A and B are large enough, the supposedly quiescent outputs can falsely trigger any inputs to other chips they are driving downstream.
The prior art has attempted to correct these kinds of ground and supply bounce problems. Different approaches have been tried, but all have achieved less than a complete solution. The most common work-around solution is to slow down the rate of change of the Vgs voltage driving the gates of transistors 12 and 14 by inserting an appropriate delay network between the buffer's input and the transistors. If the gate drive to the transistors 12 and 14 is slowed down enough, amplitudes A and B, in FIG. 2, will be reduced. However, in order to have a significant bounce reduction, a buffer driving a fifty picofarad load might have to slow its throughput delay from two nanoseconds to eight nanoseconds. The exact amount of slowdown required depends on the package pin inductance and the number of outputs that could be switching simultaneously. A delay that is long enough for a case when all outputs are switching, will be excessive for cases when fewer than that number are switching. With some devices now having more than 32 outputs, the bounce solution chosen can have a major influence on a device's high-speed performance.
A common technique employed to control ground bounce involves distributing the current running through pull-down devices. Multiple pull-down devices each handle a reduced portion of the whole current and are successively turned on via a delay chain. Consider the prior art found in U.S. Pat. No. 4,785,201 by Martinez. The circuit of Martinez uses a P-type Metal Oxide Semiconductor (PMOS) pull-up transistor and a N-type Metal Oxide Semiconductor (NMOS) pull-down transistor as a pair of strong driving elements. (The parasitic, but "unavoidable series inductance to system ground" is shown as a discrete inductor, and a matching inductor to V.sub.cc.) A PMOS pull-up transistor and a NMOS pull-down transistor form a pair of weak driving elements. The weaker pair are designed to turn on prior to the stronger pair via delays introduced by a pair of inverter transistors. The main idea is that the large current spike created when a large lumped device is turned on will be decreased in intensity if a previously activated weaker device dissipates some of the initial discharge energy. The gain of the stronger devices
can be slightly lower than would otherwise be required. The United States Patent of Boler et U.S. Pat. No. 4,638,187, avoids using a PMOS pull-down as a weaker device, and instead uses another NMOS pull-down transistor. This weaker pull-down transistor has a smaller gain than the main NMOS pull-down. The delay is introduced by an R-C network that includes a resistor (and stray capacitance), instead of an inverter chain. U.S. Pat. No. 4,777,389, by Wu et al., discloses a circuit that essentially uses the same current distribution as above, but uses a different method of achieving the delay for the second, stronger pull-down transistor. The delay in turning on the second, stronger pull-down transistor results from a closed loop control that waits for the high-to-low transition of the output to reach a certain level before a pull-down transistor is activated. This assures an adequate time spacing between the two current spikes. None of the prior art above directly monitor or control the particular electrical parameter that results in ground bounce, namely, the time rate of change of the pull-down current (di/dt). The sensitivities to process, temperature, and operating voltage also go largely neglected. The U.S. Pat. No. 4,622,482, of Ganger, directs itself to limiting the output voltage slew rate in telecommunications applications. A pair of fixed capacitors, and a pair of constant current sources, are each used to perform slew rate limiting and to insure linearity. Several undesirable consequences result from the implementation. Biasing circuits are required to provide N-bias and P-bias potentials, thereby requiring an accurate source externally and therefore extra I/O pins. Alternatively, internally generated biases would necessitate generators with large static DC currents to sustain a reasonable noise rejection ratio. A complementary pair of push-pull transistors and are never mutually exclusive because their gates are not pulled completely up to Vdd or down to Vss when intended to be off. This results in large leakage currents that are usually unacceptable in digital circuits. And since the push-pull transistors are never quite off, parasitic capacitive coupling in their gates to Vdd and Vss will cause the push-pull transistors to amplify any high-frequency noise on the Vdd and Vss supply rails. Slew-rate control is confined only to the saturation region of the output transistors when static biasing is used. Since the value of capacitors do not change to accommodate the push-pull transistors transition from their saturation region to their linear region, the linearity control fails at this stage and throughout the linear region of operation. The capacitive coupling provided by capacitors will couple any output transition back to the gate of the supposedly off transistor to cause it to turn on. While the resulting current contention has the effect of further limiting the voltage slew rate of the output, it inadvertently dumps even more transient and DC current to Vss, which actually increases ground bounce in digital circuits.
Lien, et al., in U.S. Pat. No. 4,933,574, disclose a BiCMOS output driver that is intended to maximize switching speed and to minimize ground bounce. A bipolar transistor in the output is not permitted to go into saturation. A pair of transistors, connected in an inverter configuration, develop a signal that indicates when the bipolar transistor pulls-down the output below a predetermined point. Three gate delay times after the output falls below a second predetermined level, a second transistor in parallel with the bipolar transistor is switched.
The prior art has more-or-less been directed at controlling ground bounce for channels that are actively switching their outputs from high-to-low. The popular technique, described above, is to use two output pull-down transistors to ease up on the rate of output slew from high-to-low. What is needed is a solution that addresses the problem of quiescent channels that are already low and become unsettled by local ground bounce induced by a neighboring output channel. The present invention provides such a solution.